For a given node technology, increasing integrated circuit (IC) size typically increases the functionality that can be included on a die. Unfortunately, defects often scale with die area. A large die is more likely to incorporate a defect than is a smaller die. Defects affect yield, and yield loss often increases with increasing die size. Various techniques have been developed to provide large ICs at desirable yield levels.
One approach to providing large ICs is to construct a large IC out of multiple smaller IC dice on a silicon interposer using through-silicon via (TSV) techniques. A silicon interposer is essentially a substrate to which the dice are flip-chip bonded after the silicon interposer has been processed to provide metal wiring and contacts. A silicon interposer typically has several patterned metal layers and intervening insulating layers connected to TSVs. Multiple IC dice are physically and electrically connected to the interposer with micro-bump arrays.
Many TSVs carry low-frequency signals or DC, such as a bias voltage or a ground return, and conventional TSVs are adequate for these applications. However, ICs that have radio-frequency (RF) or other high-frequency ports (e.g., pins or pads), or critical digital paths, such as a digital path with fast (e.g., 200 ps or less) rise or fall time, the high-frequency performance of a conventional TSV may be the limiting factor in the high-frequency or critical data path. For example, a high capacitance TSV may degrade a high-frequency signal, degrade rise/fall times of a digital signal, increase crosstalk between a signal on another TSV, or increase noise injection.
Shielding techniques are often used to reduce crosstalk between signal wires. For example, a conductive ground plane surrounding one wire shields that wire from unwanted crosstalk from other signal wires or from noise. Unfortunately, some shielding techniques for TSVs increase TSV capacitance. While such increased capacitance is acceptable in some TSV applications, it is undesirable in others.
Techniques for reducing TSV capacitance and crosstalk between TSVs are desirable.